1. Field of the Invention
The present invention relates to a semiconductor device manufacturing method for forming a silicide electrode of a metal insulator semiconductor field effect transistor (MISFET).
2. Background Art
Recently, miniaturization of semiconductor devices has been advancing. It requires size reduction of transistors in directions parallel to the surface of the semiconductor substrate, such as the gate dimensions, the width of the device isolation insulating film and the line width. It also requires size reduction in direction perpendicular to the surface of the semiconductor substrate, such as the height of the gate electrode and the junction depth of the source/drain diffusion layer.
On the other hand, it is desirable that a silicide film having a low resistance is formed on the gate electrode, the source/drain diffusion layer or the like to reduce the parasitic resistance of these regions.
To this end, the so-called self-aligned silicide (SALICIDE) process for forming a silicide film having a low resistance on the gate electrode, the surface of the source/drain diffusion layer or the like is adopted (see Japanese Patent Laid-Open Nos. 2005-19705 and 11-251591, for example).